Hi Matom,
Sorry, forgot about the block diagram, I need to draw that up still.
Trigger is controlled by the FPGA, the all the trigger inputs are optionally inverted, debounced, then masked, then OR'd together before feeding the trigger delay unit. A register is also OR'd into this for software activation of the trigger, which is not currently used in the software, but does work.
The addresses of interest are
TRIG_ENABLE_ADDR - 3-bits, selects enable (1=enabled) for each trigger source: Bit 0 - IO 1, Bit 1 - IO 2, Bit 3 - Input 3
TRIG_INVERT_ADDR - 3-bits, selects invert enable (1=enabled) for each trigger source: Bit 0 - IO 1, Bit 1 - IO 2, Bit 3 - Input 3
TRIG_DEBOUNCE_ADDR - 3-bits, selects debounce enable (1=enabled) for each trigger source: Bit 0 - IO 1, Bit 1 - IO 2, Bit 3 - Input 3
SEQ_CTL_ADDR, bit 0 (SEQ_CTL_SW_TRIG_MASK) is the software trigger bit, writing a 1 is like making one of the trigger inputs active. Be careful you don't clobber any of the other bits when changing this, use a read-modify-write.
Here's an example of creating a trigger from software:
UInt32 reg = camera->gpmc->read32(SEQ_CTL_ADDR);
camera->gpmc->write32(SEQ_CTL_ADDR, reg | SEQ_CTL_SW_TRIG_MASK);
camera->gpmc->write32(SEQ_CTL_ADDR, reg & ~SEQ_CTL_SW_TRIG_MASK);
Let me know if this helps.
David